Hardware accelerator implementation of colour correction algorithm

Colour correction algorithm plays an essential part in processing the colour information. Researches on various statistical methods in colour correction algorithms keep growing in order to obtain higher accuracy and reproducibility for the intended usage. Among those, Polynomial Colour Correction is...

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Main Author:	Loh, Shu Ting
Format:	Thesis
Language:	English
Published:	2020
Subjects:	TK Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.utm.my/id/eprint/93121/1/LohShuTingMSKE2020.pdf
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id	my-utm-ep.93121
record_format	uketd_dc
spelling	my-utm-ep.931212021-11-19T03:23:52Z Hardware accelerator implementation of colour correction algorithm 2020 Loh, Shu Ting TK Electrical engineering. Electronics Nuclear engineering Colour correction algorithm plays an essential part in processing the colour information. Researches on various statistical methods in colour correction algorithms keep growing in order to obtain higher accuracy and reproducibility for the intended usage. Among those, Polynomial Colour Correction is one of the common applications in practice. Nevertheless, the intensive computation and inconvenience of implementing complex algorithm using Hardware Description Language have significant impact on the timing performance especially for those urgent life-threatening diagnosis application. Through this project, a hardware accelerator is proposed to improve the timing performance of the repetitive nature in the Polynomial algorithm while maintaining its accuracy with a minimal degradation. But before designing the hardware accelerator, there is a need to investigate on the compute intensive part of the baseline algorithm. High Level Synthesis tool is used to maximize the design space exploration and effectively minimize the design time. The proposed work has included several optimization techniques such as loop unrolling, pipelining and array partitioning to further exploit the parallelism of the colour correction algorithm. Analysis on latency, total execution time, resource utilization, maximum operating frequency and accuracy with respect to software baseline is conducted to evaluate the outcome of the hardware design. At the end of the project, it is identified that the combination of all the three approaches is able to achieve the highest timing speedup of 22.05 times but at a cost of hardware resources. On the other point of view, it provides several solutions for designs with different usage and targets to achieve based on the performance and hardware cost trade-off. 2020 Thesis http://eprints.utm.my/id/eprint/93121/ http://eprints.utm.my/id/eprint/93121/1/LohShuTingMSKE2020.pdf application/pdf en public http://dms.library.utm.my:8080/vital/access/manager/Repository/vital:135987 masters Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering Faculty of Engineering - School of Electrical Engineering
institution	Universiti Teknologi Malaysia
collection	UTM Institutional Repository
language	English
topic	TK Electrical engineering Electronics Nuclear engineering
spellingShingle	TK Electrical engineering Electronics Nuclear engineering Loh, Shu Ting Hardware accelerator implementation of colour correction algorithm
description	Colour correction algorithm plays an essential part in processing the colour information. Researches on various statistical methods in colour correction algorithms keep growing in order to obtain higher accuracy and reproducibility for the intended usage. Among those, Polynomial Colour Correction is one of the common applications in practice. Nevertheless, the intensive computation and inconvenience of implementing complex algorithm using Hardware Description Language have significant impact on the timing performance especially for those urgent life-threatening diagnosis application. Through this project, a hardware accelerator is proposed to improve the timing performance of the repetitive nature in the Polynomial algorithm while maintaining its accuracy with a minimal degradation. But before designing the hardware accelerator, there is a need to investigate on the compute intensive part of the baseline algorithm. High Level Synthesis tool is used to maximize the design space exploration and effectively minimize the design time. The proposed work has included several optimization techniques such as loop unrolling, pipelining and array partitioning to further exploit the parallelism of the colour correction algorithm. Analysis on latency, total execution time, resource utilization, maximum operating frequency and accuracy with respect to software baseline is conducted to evaluate the outcome of the hardware design. At the end of the project, it is identified that the combination of all the three approaches is able to achieve the highest timing speedup of 22.05 times but at a cost of hardware resources. On the other point of view, it provides several solutions for designs with different usage and targets to achieve based on the performance and hardware cost trade-off.
format	Thesis
qualification_level	Master's degree
author	Loh, Shu Ting
author_facet	Loh, Shu Ting
author_sort	Loh, Shu Ting
title	Hardware accelerator implementation of colour correction algorithm
title_short	Hardware accelerator implementation of colour correction algorithm
title_full	Hardware accelerator implementation of colour correction algorithm
title_fullStr	Hardware accelerator implementation of colour correction algorithm
title_full_unstemmed	Hardware accelerator implementation of colour correction algorithm
title_sort	hardware accelerator implementation of colour correction algorithm
granting_institution	Universiti Teknologi Malaysia, Faculty of Engineering - School of Electrical Engineering
granting_department	Faculty of Engineering - School of Electrical Engineering
publishDate	2020
url	http://eprints.utm.my/id/eprint/93121/1/LohShuTingMSKE2020.pdf
_version_	1747818635566514176

Hardware accelerator implementation of colour correction algorithm

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