A parallel built-in self-test design for photon counting array
Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | http://eprints.utm.my/id/eprint/99566/1/PngKehJingMSKE2022.pdf |
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| Summary: | Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of a test solution for testability (DFT). This project is proposing the design of a parallel BIST circuit for a 16x1 photon counting array using 180 nm CMOS technology to improve the fault coverage and reduce testing cost. Almost all the test modules are built into the chip, an external tester will need to provide a start signal for the BIST design to start the testing process. LFSR is used for pseudo-random pattern generator whereas MISR and SISR are used as the output compactors. The BIST design adopts signature analysis to determine faulty chip. The golden signature is produced and being stored in ROM for comparison after fabrication. BIST controller acts as a controller unit (CU) that sends the control signals to every BIST functional block in each state. The entire BIST design is then integrated into the photon counting system for validation and layout generation. This project used bottom-up approach by designing the modules of BIST blocks in SystemVerilog. Performances are then analysed and evaluated by using Synopsys Design Compiler, IC compiler and PrimeTime tools. From the finding, proposed BIST design has managed to enhance in terms of functional reliability and design controllability with the use of SystemVerilog. For test latency, chip area, maximum frequency and power consumption, the design shows great improvements by 67.67 %, 32.26 %, 15.20 % and 48.89 % respectively. |
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