A parallel built-in self-test design for photon counting array
Test module’s architectures and methodologies that would maximize test capability to filter out faulty chip after fabrication is highly demanded for chip cost reduction. A high-speed frequency Built-in Self-test (BIST) module is playing an increasingly large part in overall efficiency and quality of...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2022
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/99566/1/PngKehJingMSKE2022.pdf |
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