Scheduling in high level synthesis of VLSI circuits /
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| Main Author: | |
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| Format: | Thesis Book |
| Language: | English |
| Published: |
1996.
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| Subjects: | |
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| LEADER | 00806cam a2200229 a 4500 | ||
|---|---|---|---|
| 001 | u413478 | ||
| 003 | SIRSI | ||
| 008 | 970714s1996 si v 00 1 eng m | ||
| 035 | |a ACD-4930 | ||
| 040 | |a UMM | ||
| 090 | |a TK7874.75 |b Xio | ||
| 100 | 1 | 0 | |a Xiong, Xing Rong. |
| 245 | 1 | 0 | |a Scheduling in high level synthesis of VLSI circuits / |c Xiong Xing Rong. |
| 260 | |c 1996. | ||
| 300 | |a v, 102 leaves : |b ill. ; |c 30 cm. | ||
| 502 | |a Dissertation (M.Sc.) -- National University of Singapore, 1996. | ||
| 504 | |a Bibliography: leaves 85-89. | ||
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design and construction |x Data processing. | |
| 650 | 0 | |a Computer-aided design. | |
| 948 | |a 14/07/1997 |b 08/01/1999 | ||
| 596 | |a 1 | ||
| 999 | |a TK7874.75 XIO |w LC |c 1 |i A506946765 |l STACKS |m P01UTAMA |r Y |s Y |t TESIS |u 24/10/1997 | ||