Rescheduling in high-level syntheses /
Saved in:
Main Author: | Lim, Daniel Kok Yong |
---|---|
Format: | Thesis Book |
Language: | English |
Published: |
1997.
|
Subjects: | |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Scheduling in high level synthesis of VLSI circuits /
by: Xiong, Xing Rong
Published: (1996) -
Channel routing for rectilinear and octilinear routing models /
by: Lee, James Kok Kiong
Published: (1992) -
Efficient algorithms for over-the-cell channel routing in VLSI design using two and three routing layers /
by: Shew, Paul Waie
Published: (1996) -
Steiner problem in octilinear routing model /
by: Koh, Cheng Kok
Published: (1995) -
Algorithms for reconfiguration problems in VLSI/WSI arrays /
by: Low, Chor Ping
Published: (1994)