1.0V, 10-bit, 20-MS/s pipelined analog-to-digital converter design /
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| Main Author: | |
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| Format: | Thesis Book |
| Language: | English |
| Published: |
2002.
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| LEADER | 00703cam a2200205 a 4500 | ||
|---|---|---|---|
| 001 | u505803 | ||
| 003 | SIRSI | ||
| 008 | 020917s2002 si v 00 1 eng m | ||
| 035 | |a ACW-0793 | ||
| 040 | |a UMM | ||
| 090 | |a TK7 |b NUS 2002 Leo | ||
| 100 | 1 | 0 | |a Leong, See Chuan. |
| 245 | 1 | 0 | |a 1.0V, 10-bit, 20-MS/s pipelined analog-to-digital converter design / |c Leong See Chuan. |
| 260 | |c 2002. | ||
| 300 | |a x, 101 leaves : |b ill. ; |c 30 cm. | ||
| 502 | |a Dissertation (M.Eng.) -- National University of Singapore, 2002. | ||
| 504 | |a Bibliography: leaves 85-87. | ||
| 948 | |a 24/10/2002 |b 26/12/2002 | ||
| 596 | |a 1 | ||
| 999 | |a TK7 NUS 2002 LEO |w LC |c 1 |i A510949512 |l B_KOM4 |m P01UTAMA |r Y |s Y |t TESIS |u 3/1/2003 |o .PUBLIC. BKOM 4 : 45952 | ||