Low power clock tree synthesis for ASIC VLSI design /
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| 主要作者: | |
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| 格式: | Thesis 圖書 |
| 語言: | English |
| 出版: |
2010.
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| 001 | u853386 | ||
| 003 | SIRSI | ||
| 005 | 201203190940 | ||
| 008 | 120319s2010 my a t 000 0 eng m | ||
| 040 | |a UMM |d UMJ | ||
| 090 | |a TA7 |b UM 2010 Ten | ||
| 097 | |a TA7 |b UM 2010 Ten | ||
| 100 | 1 | |a Teng, Siong Kiong. | |
| 245 | 1 | 0 | |a Low power clock tree synthesis for ASIC VLSI design / |c Teng Siong Kiong. |
| 260 | |c 2010. | ||
| 300 | |a xviii, 185 leaves : |b ill. ; |c 30 cm. | ||
| 502 | |a Dissertation (M.Eng.Sc.) -- Jabatan Kejuruteraan Elektrik, Fakulti Kejuruteraan, Universiti Malaya, 2010. | ||
| 504 | |a Bibliography: leaves 166-170. | ||
| 650 | 0 | |a Application-specific integrated circuits |x Design. | |
| 650 | 0 | |a Integrated circuits |x Very large scale integration |x Design. | |
| 650 | 0 | |a Semiconductors |x Design. | |
| 650 | 0 | |a Electronic circuit design. | |
| 710 | 2 | |a Universiti Malaya. |b Jabatan Kejuruteraan Elektrik. | |
| 900 | |a AT-ZA | ||
| 596 | |a 1 7 | ||
| 999 | |a TA7 UM 2010 TEN |w LC |c 1 |i A515697215 |d 6/1/2014 |f 6/1/2014 |g 1 |l STACKS |m P01UTAMA |r Y |s Y |t TESIS |u 31/12/2013 | ||
| 999 | |a TA7 UM 2010 TEN |w LC |c 1 |i A514904150 |d 8/4/2014 |f 8/4/2014 |g 1 |l STACKS |m P07JURUTER |r Y |s Y |t TESIS |u 21/3/2014 | ||