Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output...
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| Main Author: | |
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| Format: | Thesis |
| Language: | English |
| Published: |
2006
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| Subjects: | |
| Online Access: | https://ir.uitm.edu.my/id/eprint/102744/1/102744.pdf |
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| Summary: | This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output port pins of the 3DES from about 300 pins to 44 pins that is suited for standard packaging available in the market. The port pins allow the 3DES to communicate with outside world. Xilinx ISE™ 7.1i software is utilized to create Verilog HDL code and synthesize. The result of simulation was carrying out by ModelSim XE III 6.0a. |
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