Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin

Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin

This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output...

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Main Author: Kamal Bahrin, Nor Aizee Masyitah
Format: Thesis
Language:English
Published: 2006
Subjects:
Electric apparatus and materials
Electric circuits
Electric networks
Online Access:https://ir.uitm.edu.my/id/eprint/102744/1/102744.pdf
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spelling my-uitm-ir.1027442024-11-20T01:32:23Z Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin 2006 Kamal Bahrin, Nor Aizee Masyitah Electric apparatus and materials. Electric circuits. Electric networks This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output port pins of the 3DES from about 300 pins to 44 pins that is suited for standard packaging available in the market. The port pins allow the 3DES to communicate with outside world. Xilinx ISE™ 7.1i software is utilized to create Verilog HDL code and synthesize. The result of simulation was carrying out by ModelSim XE III 6.0a. 2006 Thesis https://ir.uitm.edu.my/id/eprint/102744/ https://ir.uitm.edu.my/id/eprint/102744/1/102744.pdf text en public degree Universiti Teknologi MARA (UiTM) Faculty of Electrical Engineering
institution Universiti Teknologi MARA
collection UiTM Institutional Repository
language English
topic Electric apparatus and materials
Electric circuits
Electric networks
spellingShingle Electric apparatus and materials
Electric circuits
Electric networks
Kamal Bahrin, Nor Aizee Masyitah
Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
description This report presents the development of interfacing circuit for Triple Data Encryption Standard (3DES) that is being designed using Verilog HDL for Field Programmable Gate Array (FPGA) implementation. The purpose of this project is to design the interfacing circuit that can minimize the input/output port pins of the 3DES from about 300 pins to 44 pins that is suited for standard packaging available in the market. The port pins allow the 3DES to communicate with outside world. Xilinx ISE™ 7.1i software is utilized to create Verilog HDL code and synthesize. The result of simulation was carrying out by ModelSim XE III 6.0a.
format Thesis
qualification_level Bachelor degree
author Kamal Bahrin, Nor Aizee Masyitah
author_facet Kamal Bahrin, Nor Aizee Masyitah
author_sort Kamal Bahrin, Nor Aizee Masyitah
title Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
title_short Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
title_full Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
title_fullStr Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
title_full_unstemmed Development of interaction circuit for triple data encryption standard (3DES) using verilog for FPGA implementation / Nor Aizee Masyitah Kamal Bahrin
title_sort development of interaction circuit for triple data encryption standard (3des) using verilog for fpga implementation / nor aizee masyitah kamal bahrin
granting_institution Universiti Teknologi MARA (UiTM)
granting_department Faculty of Electrical Engineering
publishDate 2006
url https://ir.uitm.edu.my/id/eprint/102744/1/102744.pdf
_version_ 1818588047194718208

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