Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies

ADC production testing has become more challenging due to more stringent test procedure for new generation of ADC. The trend for silicon cost is going down while the cost of test is going up. Therefore, to reduce the cost of test and preserve the test accuracy is essential for high volume testing in...

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Main Author:	Wan Ismail, Wan Mohd Fahmi
Format:	Thesis
Language:	English
Published:	2015
Subjects:	TK7800-8360 Electronics
Online Access:	http://eprints.usm.my/40967/1/WAN_MOHD_FAHMI_BIN_WAN_ISMAIL_24_pages.pdf
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id	my-usm-ep.40967
record_format	uketd_dc
spelling	my-usm-ep.409672018-07-10T08:19:12Z Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies 2015 Wan Ismail, Wan Mohd Fahmi TK7800-8360 Electronics ADC production testing has become more challenging due to more stringent test procedure for new generation of ADC. The trend for silicon cost is going down while the cost of test is going up. Therefore, to reduce the cost of test and preserve the test accuracy is essential for high volume testing in production. This research is conducted for accurate ADC testing using histogram methodologies. Histogram methodology is the most common test procedure used in high volume production testing. In the past there were a lot of studies on testing the ADC but there were no emphasizing on various histogram methodologies for high volume testing. This research objective is to develop test solutions for 28nm 10 bit ADC using histogram methodologies. The outcome from this research has clearly shows that the test program that has been developed is able to segregate the good and bad devices. 98.18% of the devices are able to pass the ADC testing while remaining 1.82% fail the ADC test. It was found that Ramp Histogram and Sinusoidal Histogram method has achieved this research objective as both methodologies shows similar result based on comparison that has been made. It was known that accurate ADC testing requires large sample size. This research found that multi-site testing was able to compensate the drawback in histogram methodologies. The result shows that multi-site testing is 63.72% more efficient in term of ADC testing time. 2015 Thesis http://eprints.usm.my/40967/ http://eprints.usm.my/40967/1/WAN_MOHD_FAHMI_BIN_WAN_ISMAIL_24_pages.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK7800-8360 Electronics
spellingShingle	TK7800-8360 Electronics Wan Ismail, Wan Mohd Fahmi Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
description	ADC production testing has become more challenging due to more stringent test procedure for new generation of ADC. The trend for silicon cost is going down while the cost of test is going up. Therefore, to reduce the cost of test and preserve the test accuracy is essential for high volume testing in production. This research is conducted for accurate ADC testing using histogram methodologies. Histogram methodology is the most common test procedure used in high volume production testing. In the past there were a lot of studies on testing the ADC but there were no emphasizing on various histogram methodologies for high volume testing. This research objective is to develop test solutions for 28nm 10 bit ADC using histogram methodologies. The outcome from this research has clearly shows that the test program that has been developed is able to segregate the good and bad devices. 98.18% of the devices are able to pass the ADC testing while remaining 1.82% fail the ADC test. It was found that Ramp Histogram and Sinusoidal Histogram method has achieved this research objective as both methodologies shows similar result based on comparison that has been made. It was known that accurate ADC testing requires large sample size. This research found that multi-site testing was able to compensate the drawback in histogram methodologies. The result shows that multi-site testing is 63.72% more efficient in term of ADC testing time.
format	Thesis
qualification_level	Master's degree
author	Wan Ismail, Wan Mohd Fahmi
author_facet	Wan Ismail, Wan Mohd Fahmi
author_sort	Wan Ismail, Wan Mohd Fahmi
title	Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
title_short	Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
title_full	Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
title_fullStr	Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
title_full_unstemmed	Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies
title_sort	evaluation of 28nm 10 bit adc using ramp and sinusoidal histogram methodologies
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuruteraan Elektrik dan Elektronik
publishDate	2015
url	http://eprints.usm.my/40967/1/WAN_MOHD_FAHMI_BIN_WAN_ISMAIL_24_pages.pdf
_version_	1747820850032148480

Evaluation Of 28nm 10 Bit Adc Using Ramp And Sinusoidal Histogram Methodologies

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