Clock Gating Technique For Power Reduction In Digital Design
Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not g...
Saved in:
| Main Author: | |
|---|---|
| Format: | Thesis |
| Language: | English |
| Published: |
2012
|
| Subjects: | |
| Online Access: | http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|