Clock Gating Technique For Power Reduction In Digital Design

Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not g...

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Main Author:	Khor, Peng Lim
Format:	Thesis
Language:	English
Published:	2012
Subjects:	TK1-9971 Electrical engineering Electronics Nuclear engineering
Online Access:	http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf
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id	my-usm-ep.44825
record_format	uketd_dc
spelling	my-usm-ep.448252019-07-03T00:58:38Z Clock Gating Technique For Power Reduction In Digital Design 2012-12 Khor, Peng Lim TK1-9971 Electrical engineering. Electronics. Nuclear engineering Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited. 2012-12 Thesis http://eprints.usm.my/44825/ http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf application/pdf en public masters Universiti Sains Malaysia Pusat Pengajian Kejuteraan Elektrik & Elektronik
institution	Universiti Sains Malaysia
collection	USM Institutional Repository
language	English
topic	TK1-9971 Electrical engineering Electronics Nuclear engineering
spellingShingle	TK1-9971 Electrical engineering Electronics Nuclear engineering Khor, Peng Lim Clock Gating Technique For Power Reduction In Digital Design
description	Power reduction techniques become increasingly important to the deep sub-micron scale digital integrated circuit (IC) design. Multiple power reduction techniques are used to keep the power consumption under control even when the operating frequency is high. Same power reduction technique might not give the same power saving efficiency when the operating frequency increases. Power reduction effectiveness decreases follows downward of the design flow. For an IC design house without fabrication factory, levels of power optimization in the design flow are very limited.
format	Thesis
qualification_level	Master's degree
author	Khor, Peng Lim
author_facet	Khor, Peng Lim
author_sort	Khor, Peng Lim
title	Clock Gating Technique For Power Reduction In Digital Design
title_short	Clock Gating Technique For Power Reduction In Digital Design
title_full	Clock Gating Technique For Power Reduction In Digital Design
title_fullStr	Clock Gating Technique For Power Reduction In Digital Design
title_full_unstemmed	Clock Gating Technique For Power Reduction In Digital Design
title_sort	clock gating technique for power reduction in digital design
granting_institution	Universiti Sains Malaysia
granting_department	Pusat Pengajian Kejuteraan Elektrik & Elektronik
publishDate	2012
url	http://eprints.usm.my/44825/1/KHOR%20PENG%20LIM.pdf
_version_	1747821406330028032

Clock Gating Technique For Power Reduction In Digital Design

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