High speed serial input/output (I/O) time and frequency characterization with correlation method
High Speed serial data bus is developed to support data transfer between the CPU and peripherals on the PC motherboard in future generation applications. At high speed with multi-gigabit, impedance mismatch between the CPU and peripherals becomes critical and limits the possible maximum throughput....
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2009
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/12362/1/NeohChaiChenMFKE2009.pdf |
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| 總結: | High Speed serial data bus is developed to support data transfer between the CPU and peripherals on the PC motherboard in future generation applications. At high speed with multi-gigabit, impedance mismatch between the CPU and peripherals becomes critical and limits the possible maximum throughput. This effect can be modeled as a convolution process where the I/O bus behaves as a linear time invariant system that is defined by a channel impulse and frequency response. Since there are variations in the characteristic of the motherboards due to the fabrication and assembly process, it is desired to estimate the impulse response and frequency response of the High Speed I/O bus. Impulse response and frequency response can be used to gate the capability of the motherboard. Correlation method is used to find out channel impulse and frequency response. In order to evaluate the capability of the correlation method under actual manufacturing environment, the evaluation was performed on data collected from actual production test and MATLAB tools will be used for post processing. PCI Express Gen 1 is used to generate high speed data at 2.5Gbps. The results show that there is no difference auto-correlation and cross-correlation in measurement data except the overshoot amplitude and time delay in due to the internal built in equalization technique. |
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