Test vectors reductoin for integrated circuit testing using horizontal hamming distance
In testing digital combinational logic for stuck-at faults, it is required to determine the most appropriate test sequence needed to detect the required number of possible faults. The exhaustive test pattern generation method is the simplest approach to implement as it produces test patterns consist...
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| 主要作者: | |
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| 格式: | Thesis |
| 語言: | English |
| 出版: |
2016
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| 主題: | |
| 在線閱讀: | http://eprints.utm.my/id/eprint/77590/1/ArbabAlamgirMFKE2016.pdf |
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